| With increasing design complexity, verification becomes a more and
more important aspect of the design flow. Modern circuits contain up
to several million transistors. In the meantime it has been observed that
verification becomes the major bottleneck, i.e. up to 80% of the overall
design costs are due to verification. This is one of the reasons why recently
several methods have been proposed as alternatives to classical
simulation, since it cannot guarantee sufficient coverage of the design.
E.g. in [2] it has been reported that for the verification of the Pentium
IV more than 200 billion cycles have been simulated, but this only corresponds
to 2 CPU minutes, if the chip is run with 1 GHz.
Formal verification techniques have gained large attention, since they
allow to prove the correctness of a circuit, i.e. they ensure 100% functional
correctness. Besides being more reliable, formal verification approaches
have also shown to be more cost effective in many cases, since
test bench creation - usually a very time consuming and error prone task
- becomes superfluous. |
