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Verification Techniques for System-Level Design (Systems on Silicon)

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A must-read in formal and semi-formal verification!

This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs.

First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs.

Formal verification of high-level designs (RTL or higher).

Verification techniques are discussed with associated system-level design methodology.

About the Author

Mukul Prasad received the Bachelor of Technology degree in Electrical Engineering from the Indian Institute of Technology, Delhi, India, in 1995, and the Ph.D. degree in Electrical Engineering & Computer Sciences from the University of California at Berkeley in 2001.

Since 2001 he has been a member of the research staff in the Trusted Systems Innovation group at Fujitsu Laboratories of America in Sunnyvale, California. His doctoral thesis and his subsequent research has involved the development and application of verification technologies such as Satisfiability solvers. His work has received a Best Paper Award at the Design Automation & Test in Europe Conference (DATE 2002). His current research addresses various problems in system-level design validation. He has co-authored more than 20 technical papers and presented three tutorials at international conferences and jointly holds 3 U.S. patents in the area of formal validation.
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