With the availability of chips offering constantly increasing computational performance and
functionality, design of more and more complex applications becomes possible. This is particularly
true for the domain of image processing, which is characterized by huge computation
efforts. Unfortunately, this evolution risks to be stopped by the fact that employed design
methodologies remain on a rather low level of abstraction. The resulting design gap causes
increasing development costs or even project failure and thus threatens the technical progress.
Consequently, new design methodologies are urgently required. A corresponding review
about the state of the art reveals that different approaches are competing in order to solve
the above-mentioned challenges. The proposed techniques range from behavioral compilers
accepting standard C or Matlab code as input, over block-based design methods such as
Simulink and SystemC, to data flow specifications and polyhedral analysis. Each of them
offers important benefits, such as quick and easy hardware prototyping, higher levels of
abstractions, and enhanced system and algorithm analysis on different levels of granularity.
However, a solution combining the advantages of all these approaches is still missing. As a
consequence, system level design of image processing applications still causes various challenges.
Corresponding examples are the lack to handle the resulting system complexity or to
cover important algorithmic properties. Equally, the synthesis of high-performance hardware
implementations is still difficult.
Fortunately, recent research is able to demonstrate that multidimensional data flow seems
to be a promising technique solving these drawbacks, because it combines the advantages
of block-based specification, data flow-related system analysis, and polyhedral optimization
on different levels of granularity. These benefits enable, for instance, the verification of the
application specification on a very high level of abstraction, the calculation of required memory
sizes for correct algorithm implementation considering different design tradeoffs, and
the synthesis of high-performance communication infrastructures and algorithm implementations.