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Higher-Level Hardware Synthesis

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Higher-Level Hardware Synthesis, 9783540213062 (3540213066), Springer, 2004
In the mid 1960s, when a single chip contained an average of 50 transistors,
Gordon Moore observed that integrated circuits were doubling in complexity
every year. In an influential article published by Electronics Magazine in 1965,
Moore predicted that this trend would continue for the next 10 years. Despite
being criticized for its “unrealistic optimism,” Moore’s prediction has remained
valid for far longer than even he imagined: today, chips built using state-ofthe-
art techniques typically contain several million transistors. The advances in
fabrication technology that have supported Moore’s law for four decades have
fuelled the computer revolution. However, this exponential increase in transistor
density poses new design challenges to engineers and computer scientists alike.
New techniques for managing complexity must be developed if circuits are to
take full advantage of the vast numbers of transistors available.

In this monograph we investigate both (i) the design of high-level languages
for hardware description, and (ii) techniques involved in translating these highlevel
languages to silicon. We propose SAFL, a first-order functional language
designed specifically for behavioral hardware description, and describe the implementation
of its associated silicon compiler. We show that the high-level properties
of SAFL allow one to exploit program analyses and optimizations that
are not employed in existing synthesis systems. Furthermore, since SAFL fully
abstracts the low-level details of the implementation technology, we show how it
can be compiled to a range of different design styles including fully synchronous
design and globally asynchronous locally synchronous (GALS) circuits.
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