The scaling of silicon technology has been ongoing for over forty years. We are on our way to commercializing devices having a minimum feature size of one-tenlh of a micron. The push for miniaturization comes from the demand for higher functionality and higher performance at a lower cost. As a result, successively higher levels of integration have been driving up the power consumption of chips. Today heat removal and power distribution are at the forefront of the problems faced by chip designers.

In recent years portability has become important. Historically, portable applications were characterized by low throughput requirements such as for a wristwatch. This is no longer true. Among the new portable applications are hand-held multimedia terminals with video display and capture, audio repro- duction and capture, voice recognition, and handwriting recognition capabili- ties. These capabilities call for a tremendous amount of computational capacity. This computational capacity has to be realized with very low power requirements in order for the battery to have a satisfactory life span. This book is an attempt to provide the reader with an in depth understanding of the sources of power dissipation in digital CMOS circuits and to provide techniques for the design of low-power circuit chips with high computational capacity.