| Continuing advances in chip technology, such as the ability to place more
transistors on the same die (together with increased operating speeds) have
opened new opportunities in embedded applications, breaking new ground in
the domains of communication, multimedia, networking and entertainment.
New consumer products, together with increased time-to-market pressures have
created the need for rapid exploration tools to evaluate candidate architectures
for System-On-Chip (SOC) solutions. Such tools will facilitate the introduction
of new products customized for the market and reduce the time-to-market for
such products.
While the cost of embedded systems was traditionally dominated by the
circuit production costs, the burden has continuously shifted towards the design
process, requiring a better design process, and faster turn-around time. In
the context of programmable embedded systems, designers critically need the
ability to explore rapidly the mapping of target applications to the complete
system. Moreover, in today’s embedded applications, memory represents a
major bottleneck in terms of power, performance, and cost.
The near-exponential growth in processor speeds, coupled with the slower
growth in memory speeds continues to exacerbate the traditional processormemory
gap. As a result, the memory subsystem is rapidly becoming the
major bottleneck in optimizing the overall system behavior in the design of
next generation embedded systems. In order to match the cost, performance,
and power goals, all within the desired time-to-market window, a critical aspect
is the Design Space Exploration of the memory subsystem, considering all
three elements of the embedded memory system: the application, the memory
architecture, and the compiler early during the design process. |
