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Layout generation is an important topic in IC design. For digital circuits a lot of research
has been conducted in this area, resulting in a large variety of books and layout generation
tools. However, with the ever increasing frequencies, we are facing now significant analog
types of artifacts in the IC, introduced during the physical design phase, when schematics are
translated to physical ICs via a layout. Moreover, with the trend to systems on chip, analog
circuitry and massive amounts of digital circuitry are going to be integrated on the same chip,
now called a mixed-signal chip. Compatibility between the high-resolution but low-level
analog signals and the relatively large-swing digital signals with their fast transition edges is
becoming a severe problem, which makes layout generation a tedious and complex job.
In this book we focus on two strongly coupled aspects of automatic layout generation,
placement and routing. We will discuss the problem in detail in the context of mixed-signal
designs. Apart from the physical artifacts and their parasitic influence on the electrical behaviour
of the circuit, we will address aspects related to the optimization problem associated
with automatic layout generation. These are the optimization methods, with special emphasis
on simulated annealing; adequate data structures; appropriate models and representations;
and efficient algorithms. As optimization is an iterative process, incremental algorithms that
only generate strictly necessary new information are especially interesting to speed up the
process. These algorithms get special attention.
The book can be seen as a combination of introductory texts and results of new research.
Therefore it will be interesting for designers that like to get an overall picture, and for experts
in the field who like to see the state of the art, and who will be interested in the new topics
discussed in this book. Moreover, it is interesting both for designers and specialists in the area
of circuit design and for those working in the area of electronic design automation (EDA).
From the new contributions we will mention only a few selected issues here. A novel incremental
approach to placement optimization is presented, featuring significantly improved
asymptotic computational complexity results for a single placement computation within a
simulated-annealing environment. A new consistent linear-time algorithm is described that
maps a given placement of modules in a user-specified region to an efficient formal representation,
such that the information can be further processed by means of efficient algorithms.
Efficiency is an important issue for CAD tools. An improved robust placement algorithm is
addressed. The algorithm can incorporate range and boundary constraints that are imposed
on specific modules in a very efficient manner. Further, a framework is given that incorporates
placement and routing, making it easy to take into account physical problems that are
related to the spatial distribution of objects in a plane, which in this case is the plane of the IC.
New results are shown on very fast Steiner-minimal-tree approximation algorithms in combination
with efficient dynamic routing graph models. Extensive experimental evaluations of
the proposed algorithms show that our algoritms compare favorably with the state of the art.
This title covers important physical-design issues that exist in contemporary analogue and mixed-signal design flows. The authors bring together many principles and techniques required to successfully develop and implement layout generation tools to accommodate many mixed-signal layout generation needs. |
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