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On-Chip Communication Architectures: System on Chip Interconnect (Systems on Silicon)

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Digital electronic devices such as mobile phones, video game consoles, and network routers typically contain one or more electronic (integrated circuit) chips that are composed of several components such as processors, dedicated hardware engines and memory, and are referred to as system-on-chip (SoC). These SoC designs are rapidly becoming more complex, in order to handle the ever increasing complexity of applications, fueled by the onset of the digital convergence era. Continuing improvements in process technology have allowed the integration of components previously connected at the board level onto a single chip, which further adds to the complexity.

The components on a SoC are connected together by an on-chip communication architecture backbone that supports all inter-component data communication, both within the chip as well as with external devices (e.g., external fl ash drives). These SoC communication architectures have been shown to have a significant impact on the performance, power consumption, cost, and design time of SoCs. Indeed, modern SoC design processes are increasingly becoming communication- centric, since reusable components (e.g., processors, memories, etc.), as well as custom hardware blocks and interfaces, need to be connected via a communication architecture fabric, with the goal of meeting various design constraints such as cost, performance, power/energy, and reliability. The move toward higher levels of abstraction have led to the notion of electronic system level (ESL) design, where system architects and application designers are able to capture system functionality and map desired system functionality onto a range of software and hardware confi gurations that exhibit differing performance, cost, power/ energy, reliability, and other design metrics. A key step within an ESL design fl ow is the effi cient use of an on-chip communication architecture fabric. Consequently, there has been a large body of work on modeling abstractions, communication protocols and standards, as well as active research on communication architecture design and exploration.

This book aims to serve as a comprehensive reference on the concepts, research, and trends in on-chip communication architecture design. We describe the basic concepts and attributes of on-chip communication architectures, to familiarize the reader with intricate details of on-chip communication architecture design and the problems facing designers. This is followed by an expansive survey of research efforts in this area, spanning the past several years, and addressing some of the major issues in on-chip communication architecture design. Finally, we present some of the trends that will shape future research in the area of onchip communication architecture design.

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