Faced with the steadily increasing complexity and rapidly shortening timeto-
market requirements designing electronic systems is a very challenging task.
To manage this situation effectively the level of abstraction in modeling has
been raised during the past years in the computer aided design community.
Meanwhile, for the so-called system-level design the system description language
SystemC has become the de facto standard. However, while modeling
from abstract to synthesizable descriptions in combination with specification
concepts like Transaction Level Modeling (TLM) leads to very good results,
the verification quality is poor. The two main reasons are that (1) the existing
SystemC verification techniques do not escort the different abstraction levels
effectively and (2) in particular the resulting quality in terms of the covered
functionality is only checked manually. Hence, due to the increasing design
complexity the number of undetected errors is growing rapidly.
Therefore a quality-driven design and verification flow for digital systems
is developed and presented in this book. Two major enhancements characterize
the new flow: First, dedicated verification techniques are integrated which
target the different levels of abstraction. Second, each verification technique is
complemented by an approach to measure the achieved verification quality.
The new flow distinguishes three levels of abstraction (namely system level,
top level and block level) and can be incorporated in existing approaches. After
reviewing the preliminary concepts, in the following chapters the three levels
for modeling and verification are considered in detail. At each level the
verification quality is measured. In summary, following the new design and
verification flow a high overall quality results.