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Standard for VHDL Register Transfer Level (Rtl) Synthesis

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[This introduction is not part of IEEE Std 1076.6-1999, IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis.]

This standard describes a syntax and semantics for VHDL RTL synthesis. It defines the subset of IEEE Std 1076-1993 (VHDL) that is suitable for RTL synthesis as well as the semantics of that subset for the synthesis domain. This standard is based on IEEE Std 1076-1993, IEEE Std 1164-1993, and IEEE Std 1076.3-1997.

The purpose of this standard is to define a syntax and semantics that can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools use IEEE Std 1076-1993. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of a particular synthesis implementation by making their designs compliant with this standard.

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