|
Design of microprocessor and/or multimicroprocessor systems represents a continuous struggle; success (if achieved) lasts infinitesimally long and disappears forever, unless a new struggle (with unpredictable results) starts immediately. In other words, it is a continuous sur-vival process, which is the main motto of this book.
This book is about survival of those who have contributed to the state of the art in the rap-idly changing field of microprocessing and multimicroprocessing on a single chip, and about the concepts that have to find their way into the next generation microprocessors and multim-icroprocessors on a chip, in order to enable these products to stay on the competitive edge.
This book is based on the assumption that the ultimate goal of the single chip design is to have an entire distributed shared memory system on a single silicon die, together with numer-ous specialized accelerators, including the complex ones of SIMD and/or MISD type. Conse-quently, the book concentrates on the major problems to be solved on the way to this ultimate goal (distributed shared memory on a single chip), and summarizes the author’s experiences which led to such a conclusion (in other words, the problem is how to “invest one billion tran-sistors” on a single chip).
This book is also about the microprocessor and multimicroprocessor based designs of the author himself, and about the lessons that he has learned through his own professional sur-vival process which lasts for about two decades now; concepts from microprocessor and mul-timicroprocessor boards of the past represent potential solutions for the microprocessor and multimicroprocessor chips of the future, and (which is more important) represent the ground for the author’s belief that the ultimate goal is to have an entire distributed shared memory on a single chip, together with numerous specialized accelerators.
At first, distributed shared memory on a single chip may sound as a contradiction; however, it is not. As the dimensions of chips become larger, their full utilization can be obtained only with multimicroprocessor architectures. After the number of microprocessors reaches 16, the SMP architecture is no longer a viable solution since bus becomes a bottleneck; consequently, designers will be forced to move to the distributed shared memory paradigm (implemented in hardware, or partially in hardware and partially in software). |