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System-on-a-Chip: Design and Test

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This project started as an interim report. The purpose was to communicate
to various groups within Advantest about the main issues for system-on-achip
(SoC) design and testing and the common industrial practices. Over
one year’s time, a number of people contributed in various capacities to complete
this report.

During this period, I also participated in the Virtual Socket Interface
(VSI) Alliance’s effort to develop various specification documents related
to SoC design and testing and in the IEEE P1500 working group’s effort
to develop a standard for core testing. As a result of this participation, I
noticed that SoC information is widely scattered and many misconceptions
are spread throughout the community, from misnamed terms to complete
conceptual misunderstanding. It was obvious that our interim report would
be quite useful for the community as a general publication.

With that thought, I contacted Artech House. The editorial staff at
Artech House had already been hearing and reading a lot about system-ona-
chip and was very excited about this project. Considering the rapid technology
changes, a four-month schedule was prepared and I set out to prepare
the manuscript before the end of 1999. Although I had the baseline material
in the form of an interim report, simple editing was not enough. Besides the
removal of some sections from the report, many sections and even chapters
required a complete overhaul and new write-ups. Similarly, a couple of new
chapters were needed. Because of the very aggressive schedule and other
internal projects, at times it felt very tedious and tiring. This may have
resulted in incomplete discussions in a few sections. I was able to fix
descriptions in some sections based on feedback from my colleagues at ARD
and from Artech reviewers, but readers may find a few more holes in the text.
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