| With the advent of nanometer technologies, circuit performance constraints are becoming ever more stringent. In this context, automated timing analysis and optimization becomes imperative for the design of high-performance circuits that must satisfy a demanding set of constraints. Timing overviews the state of the art in timing analysis and optimization, and is intended to serve as a compendium that can provide an introduction to the uninitiated reader, as a ready reference for a practitioner, or as a source for the accomplished researcher. A comprehensive overview of the basics of timing analysis is provided, and this is augmented with techniques that incorporate physical effects arising in deep submicron and nanometer technologies. The book provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levels. The intended audience includes CAD tool developers, graduate students, research professionals, and the merely curious.
It is customary to begin a book of this sort with Deep and Noble Thoughts. There are a number of excellent sources that convincingly make the point that timing is extremely important in current and future technologies‚ and as a Bear of Very Little Brain [Mil28]‚ the author has little to add to this. Therefore‚ all that there is to say is presented in a hybrid between a preface and an introduction (which‚ in case you were wondering‚ is where the title of this chapter came from). Suffice it to say that if you’ve picked up this book‚ you’re probably interested in timing in one way or another.
This book attempts to provide an overview of methods that are used for the analysis and optimization of timing in digital integrated circuits in contemporary technologies. It is rather well known that this topic is important to circuit designers and CAD engineers. The problem of timing analysis and optimization has come a long way over the years‚ and has become increasingly complicated with the passage of time due to two classes of effects that arise due to shrinking device geometries:
“Micro” effects correspond to new physical effects at the device or interconnect level caused by reductions in device dimensions.
“Macro” effects are related to problems of scale‚ as circuit sizes increase with the ability to pack larger circuits on a die. |
