Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Describes state-of-the-art verification methodologies
Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling
Introduces you to the Programming Language Interface (PLI)
Describes logic synthesis methodologies
Explains timing and delay simulation
Discusses user-defined primitives
Offers many practical modeling tips
Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter.
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